Xinghua Wang

Orcid: 0000-0003-1825-7595

Affiliations:
  • Beijing Institute of Technology, Beijing, China


According to our database1, Xinghua Wang authored at least 26 papers between 2013 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Quantum transformers for image classification: integrating variational quantum circuits and quantum wavelet KAN.
Quantum Mach. Intell., June, 2026

Fama: An FPGA-Oriented Multiscalar Multiplication Accelerator Optimized via Algorithm-Hardware Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

A 28-nm 88.3-TFLOPS/W POSIT-Approximate-Calculation-Based Digital Computing-in-Memory Macro Incorporating Final-Cycle Fusion and Joint Skipping.
IEEE J. Solid State Circuits, April, 2026

2025
A 7.2-16 GHz 50%-LO Receiver With Enhanced Linearity and High Dynamic Range in 55-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity.
IEEE J. Solid State Circuits, January, 2025

14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

Design and Implementation of Broadband Real-time Spectrum Analysis System Based on FPGA.
Proceedings of the 2025 4th International Conference on Big Data, 2025

2024
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023

An N-Path Sub-GHz Ultra-Low Power Receiver Exploiting an N-Path Notch Filter Topology in 90 nm CMOS.
IEEE Access, 2023

2022
Design of a Time Detector with Adjustable Resolution.
Proceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering, 2022

2021
Design of a Wideband dB-Linear Variable Gain Amplifier With Continuous Gain Adjusting in 90-nm CMOS Technology.
IEEE Access, 2021

A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2018
Fast intra coding based on CU size decision and direction mode decision for HEVC.
Multim. Tools Appl., 2018

A 0.6V, 8.4uW AFE circuit for biomedical signal recording.
Microelectron. J., 2018

A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A CMOS digital step X-type attenuator with low process variations.
IEICE Electron. Express, 2017

DOA estimation based on the difference and sum coarray for coprime arrays.
Digit. Signal Process., 2017

A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2013
Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration.
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013

Circuit Design of Analog Front-End for Neural Signal Detection.
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013

A Whole Integrated System for Detection of Neural Signal and Wireless Transmission.
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013

Design and Implementation of a Circuit System for Neural Signal Detection.
Proceedings of the 2013 IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings) and IEEE Cyber, 2013


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