Xinyu Liu
Orcid: 0000-0003-0854-8559Affiliations:
- Chinese Academy of Sciences, Institute of Microelectronics, Beijing, China
According to our database1,
Xinyu Liu
authored at least 36 papers
between 2014 and 2025.
Collaborative distances:
Collaborative distances:
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Online presence:
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on orcid.org
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Bibliography
2025
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, July, 2025
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., May, 2025
A Depletion-Mode GaN-Based Envelope Tracking Supply Modulator Utilizing a Novel Coupled PWM Generator.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment.
IEEE J. Solid State Circuits, March, 2025
Microelectron. J., 2025
A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier.
Microelectron. J., 2025
Microelectron. J., 2025
A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS.
Microelectron. J., 2025
IEICE Electron. Express, 2025
A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS.
IEICE Electron. Express, 2025
An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process.
IEICE Electron. Express, 2025
IEICE Electron. Express, 2025
IEEE Access, 2025
2024
A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2024
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR.
IEEE Trans. Very Large Scale Integr. Syst., September, 2024
A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT.
Microelectron. J., January, 2024
Microelectron. J., 2024
A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity.
IEICE Electron. Express, 2024
A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC.
IEICE Electron. Express, 2024
2023
A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2021
A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEICE Electron. Express, 2019
IEICE Electron. Express, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2017
IEICE Electron. Express, 2017
Sci. China Inf. Sci., 2017
2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2014
Sci. China Inf. Sci., 2014