Qing Dong

Affiliations:
  • University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA


According to our database1, Qing Dong authored at least 29 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2021
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.
IEEE J. Solid State Circuits, 2021

2020
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation.
IEEE J. Solid State Circuits, 2020

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.
IEEE J. Solid State Circuits, 2019

A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security.
IEEE J. Solid State Circuits, 2018

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles.
IEEE J. Solid State Circuits, 2018

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin.
IEEE J. Solid State Circuits, 2018

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 0.04MM<sup>3</sup>16NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

Exploiting the analog properties of digital circuits for malicious hardware.
Commun. ACM, 2017

9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.3 A 553F<sup>2</sup> 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Rectified-linear and recurrent neural networks built with spin devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 1.02nW PMOS-only, trim-free current reference with 282ppm/°C from -40°C to 120°C and 1.6% within-wafer inaccuracy.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A2: Analog Malicious Hardware.
Proceedings of the IEEE Symposium on Security and Privacy, 2016

2015
A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.
Proceedings of the Symposium on VLSI Circuits, 2015

14.2 A physically unclonable function with BER<sup>-8</sup> for robust chip authentication using oscillator collapse in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Racetrack converter: A low power and compact data converter using racetrack spintronic devices.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014


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