Yoshinori Kohama

According to our database1, Yoshinori Kohama authored at least 10 papers between 2008 and 2011.

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Bibliography

2011
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2010

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE J. Solid State Circuits, 2010

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.
IEEE J. Solid State Circuits, 2010

2009
A High-Speed Inductive-Coupling Link With Burst Transmission.
IEEE J. Solid State Circuits, 2009

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
An 11Gb/s Inductive-Coupling Link with Burst Transmission.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008


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