Youming Yang

Orcid: 0009-0009-0593-4842

Affiliations:
  • Peking University, Beijing, China


According to our database1, Youming Yang authored at least 19 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
EA-HWP: An Efficient CNN/SNN Accelerator With Hybrid Weight Precision.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2026

A RISC-V based heterogeneous neuromorphic system with dynamic reconfigurable computing for edge AI.
Microelectron. J., 2026

A 28nm Mode-Reconfigurable CAM-CIM Hybrid Complete 3-SAT Solver Supporting Conflict-Driven Clause Learning with 100% Solvability.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

DyNeuro: A Hybrid Neuromorphic Accelerator with Dynamic Spatio-Temporal Variation Adaptations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 28-nm Optical Flow Estimation Accelerator with Redundancy Speculation, Bit-Width-Aware Compression and Similarity Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

A Multiscale Neural Interface SoC with 89.5-dB DR 4.54μW Analog Frontend and 0.00013 mm<sup>2</sup>/Ch Spatiotemporal Spike Feature Extractor.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
A Bit-Partitioned Floating-Point 6T SRAM Computing-in-Memory Macro Based on Dual-Edge Time-Domain Structure.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025

UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025

A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing.
IEEE J. Solid State Circuits, May, 2025

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm.
IEEE J. Solid State Circuits, February, 2025

A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure.
IEEE Solid State Circuits Lett., 2025

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network.
IEEE Trans. Very Large Scale Integr. Syst., December, 2024

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
An Efficient Spiking Neural Network Accelerator with Sparse Weight.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023


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