Young-Chan Jang
Orcid: 0000-0001-8680-9270
According to our database1,
Young-Chan Jang
authored at least 40 papers
between 2006 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber.
IEEE Trans. Very Large Scale Integr. Syst., April, 2024
2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme.
Proceedings of the 19th International SoC Design Conference, 2022
2021
A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor.
Sensors, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration.
Proceedings of the 18th International SoC Design Conference, 2021
2020
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization.
IEEE Trans. Circuits Syst., 2020
2019
IEEE Trans. Consumer Electron., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range.
IEICE Electron. Express, 2019
2018
Proceedings of the International SoC Design Conference, 2018
2017
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.
IEEE Trans. Consumer Electron., 2017
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display.
IEICE Trans. Electron., 2017
Proceedings of the International SoC Design Conference, 2017
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators.
IEICE Trans. Electron., 2016
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.
IEICE Trans. Electron., 2016
2014
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
IEICE Trans. Electron., 2014
A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces.
IEICE Trans. Electron., 2014
A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications.
IEICE Trans. Electron., 2014
2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2012
A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter.
J. Inform. and Commun. Convergence Engineering, 2012
A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance.
J. Inform. and Commun. Convergence Engineering, 2012
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
2011
IEICE Trans. Electron., 2011
A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Trans. Electron., 2011
2010
A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination.
IEICE Trans. Electron., 2010
An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system.
IEICE Electron. Express, 2010
A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme.
IEICE Electron. Express, 2010
2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron., 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006