Young-Chan Jang

According to our database1, Young-Chan Jang authored at least 31 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization.
IEEE Trans. Circuits Syst., 2020

A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface.
IEEE Trans. Consumer Electron., 2019

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range.
IEICE Electron. Express, 2019

12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration.
Proceedings of the International SoC Design Conference, 2018

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2.
IEEE Trans. Consumer Electron., 2017

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display.
IEICE Trans. Electron., 2017

A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver.
Proceedings of the International SoC Design Conference, 2017

0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators.
IEICE Trans. Electron., 2016

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis.
IEICE Trans. Electron., 2016

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle.
IEICE Trans. Electron., 2014

A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces.
IEICE Trans. Electron., 2014

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications.
IEICE Trans. Electron., 2014

An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter.
J. Inform. and Commun. Convergence Engineering, 2012

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance.
J. Inform. and Commun. Convergence Engineering, 2012

Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk.
IEICE Trans. Electron., 2012

A true single-phase clocked flip-flop with leakage current compensation.
IEICE Electron. Express, 2012

A Bootstrapped Analog Switch with Constant On-Resistance.
IEICE Trans. Electron., 2011

A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface.
IEICE Trans. Electron., 2011

A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination.
IEICE Trans. Electron., 2010

An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system.
IEICE Electron. Express, 2010

A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme.
IEICE Electron. Express, 2010

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron., 2007

A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006