Yuan Pu

Orcid: 0000-0002-1322-5642

Affiliations:
  • Chinese University of Hong Kong (CUHK), Department of Computer Science and Engineering, Sha Tin, Hong Kong


According to our database1, Yuan Pu authored at least 15 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
IncreMacro: Incremental Macro Placement Refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling.
ACM Trans. Design Autom. Electr. Syst., May, 2025

UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings.
CoRR, May, 2025

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

Large Language Models for EDA: From Assistants to Agents.
Found. Trends Electron. Des. Autom., 2025

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
Proceedings of the 2025 International Symposium on Physical Design, 2025

Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment.
Proceedings of the Thirteenth International Conference on Learning Representations, 2025

2024
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.
Proceedings of the 2024 International Symposium on Physical Design, 2024

IncreMacro: Incremental Macro Placement Refinement.
Proceedings of the 2024 International Symposium on Physical Design, 2024

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

NeuroSelect: Learning to Select Clauses in SAT Solvers.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract).
Proceedings of the Thirty-Second International Joint Conference on Artificial Intelligence, 2023

Restructure-Tolerant Timing Prediction via Multimodal Fusion.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023


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