Ziyi Wang

Orcid: 0000-0002-1694-5047

Affiliations:
  • Chinese University of Hong Kong, Department of Computer Science and Engineering, Sha Tin, Hong Kong


According to our database1, Ziyi Wang authored at least 22 papers between 2021 and 2026.

Collaborative distances:

Timeline

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Bibliography

2026
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
ACM Trans. Design Autom. Electr. Syst., May, 2026

DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

Prerouting Timing Prediction Across Different Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2025

Sign-Off Timing Considerations via Concurrent Routing Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2025

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits.
CoRR, February, 2025

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2025

GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays.
Proceedings of the 2025 International Symposium on Physical Design, 2025

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.
Proceedings of the 2025 International Symposium on Physical Design, 2025

NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

2024
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR, 2024

Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

Large circuit models: opportunities and challenges.
Sci. China Inf. Sci., 2024

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs.
Proceedings of the 2024 International Symposium on Physical Design, 2024

Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Restructure-Tolerant Timing Prediction via Multimodal Fusion.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Functionality matters in netlist representation learning.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Graph Learning-Based Arithmetic Block Identification.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021


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