Zhiang Wang

Orcid: 0000-0002-6669-9702

According to our database1, Zhiang Wang authored at least 35 papers between 2021 and 2026.

Collaborative distances:

Timeline

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Bibliography

2026
PigMap2: A Physical Information-Guided Technology Mapping Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2026

Invited: Post-Placement Buffering and Sizing Contest.
Proceedings of the 2026 International Symposium on Physical Design, 2026

Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research.
Proceedings of the 2026 International Symposium on Physical Design, 2026

Layout-Aware Standard Cell Synthesis via Reparameterization Multi-Task Bayesian Optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

RC-Scaled Timing-Driven Routing: Bridging Targeted Timing Optimization and Massively.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

PhySeqForm: A Data-Driven, Physical Synthesis Sequence Former.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

LSMC Meets GPU Acceleration: Scalable and High-Quality Multi-Row Detailed Placement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

HOLMES: Hierarchical Optimization with poLygonal ModEling for Large-Scale AMS Placement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A 230GHz, 128-unit Zero-IF Phased Array RX utilizing 1-D SSPLL and DTC Phase Shifter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

PigMap3: A Physically Aware Incremental Mapping Framework with On-the-fly Post-Layout Critical Path Tracking.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
Re<sup>2</sup>MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating
CoRR, November, 2025

ChipletPart: Scalable Cost-Aware Partitioning for 2.5D Systems.
CoRR, July, 2025

DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025

Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators.
ACM Trans. Design Autom. Electr. Syst., 2025

Recursive Learning-Based Virtual Buffering for Analytical Global Placement.
Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

ORFS-agent: Tool-Using Agents for Chip Design Optimization.
Proceedings of the 7th ACM/IEEE Symposium on Machine Learning for CAD, 2025

Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Use Cases and Deployment of ML in IC Physical Design.
Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

Physical Design Methods and Research Infrastructure for Machine Learning Accelerators
PhD thesis, 2024

An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators.
ACM Trans. Design Autom. Electr. Syst., 2024

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Strengthening the Foundations for IC Physical Design and ML EDA Research.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

2023
SPV-SSD: An Anchor-Free 3D Single-Stage Detector with Supervised-PointRendering and Visibility Representation.
Remote. Sens., January, 2023

Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations.
CoRR, 2023

K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement.
CoRR, 2023

Assessment of Reinforcement Learning for Macro Placement.
Proceedings of the 2023 International Symposium on Physical Design, 2023

Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021


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