Zhongyuan Zhao

Orcid: 0000-0002-6637-553X

Affiliations:

Cornell University, School of Electrical and Computer Engineering, Ithaca, NY, USA
Shanghai Jiao Tong University, Department of Micro/Nano Electronics, China

According to our database¹, Zhongyuan Zhao authored at least 11 papers between 2015 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2024

UniSparse: An Intermediate Language for General Sparse Format Customization.

[BibT_eX]

[DOI]

CoRR, 2024

2022

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2020

2019

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

Optimizing the data placement and transformation for multi-bank CGRA computing system.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A static-placement, dynamic-issue framework for CGRA loop accelerator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

2015

Resource-saving compile flow for coarse-grained reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework.

[BibT_eX]

[DOI]

Weiguang Sheng

Zhongyuan Zhao

Zhigang Mao

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

Zhongyuan Zhao

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