Blair Fort

According to our database, Blair Fort authored at least 11 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems.

Bain Syrowik, Blair Fort, Stephen Dean Brown

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

2017

FISH: Linux system calls for FPGA accelerators.

Kevin Nam, Blair Fort, Stephen Dean Brown

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

LegUp High-Level Synthesis.

Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the FPGAs for Software Programmers, 2016

2014

Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.

Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

From C to Blokus Duo with LegUp high-level synthesis.

Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

From software to accelerators with LegUp high-level synthesis.

Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson

Proceedings of the International Conference on Compilers, 2013

2006

A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification.

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Multithreaded Soft Processor for SoPC Area Reduction.

Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005

Experiences with Soft-Core Processor Design.

Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Designing an FPGA SoC Using a Standardized IP Block Interface.

Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005