Alan C. Seabaugh

Orcid: 0000-0001-6907-4129

Affiliations:
  • University of Notre Dame, USA


According to our database1, Alan C. Seabaugh authored at least 19 papers between 1993 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to high speed and nanoelectronic device and circuit technology.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory: Implications for Partial State Storage.
Proceedings of the Device Research Conference, 2022

2020
A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Process Dependent Switching Dynamics of Ferroelectric Hafnium Zirconate.
Proceedings of the Device Research Conference, 2019

Steep Subthreshold Swing Originating from Gate Delay.
Proceedings of the Device Research Conference, 2019

Dynamics of Ferroelectric and Ionic Memories: Physics and Applications.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Electric Double Layer Esaki Tunnel Junction in a 40-nm-Length, WSe2 Channel Grown by Molecular Beam Epitaxy on Al203.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

Supercapacity (>1000 fJF/cm<sup>2</sup>) charge release in a CVD-grown WSe2 FET incorporating a PEO: CsCI04 side gate.
Proceedings of the 76th Device Research Conference, 2018

Cockcroft-Walton Multiplier based on Unipolar Ag/HfO<sub>2</sub>/Pt Threshold Switch.
Proceedings of the 76th Device Research Conference, 2018

2017
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Steep slope transistors: Tunnel FETs and beyond.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2011
Fundamentals and current status of steep-slope tunnel field-effect transistors.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Low-Voltage Tunnel Transistors for Beyond CMOS Logic.
Proc. IEEE, 2010

Device and Architecture Outlook for Beyond CMOS Switches.
Proc. IEEE, 2010

2005
Design approach using tunnel diodes for lowering power in differential comparators.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

2000
Tunnel diode integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Special Issue On Quantum Devices And Their Applications.
Proc. IEEE, 1999

Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz Domain.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter.
IEEE J. Solid State Circuits, 1998

1993
Multiple-Valued Logic Computation Circuits Using Micro- and Nanoelectronic Devices.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993


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