Alejandro Suanes

Orcid: 0000-0002-6793-1147

According to our database1, Alejandro Suanes authored at least 5 papers between 2020 and 2023.

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Bibliography

2023

2022
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs.
Integr., 2022


2021
A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020


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