Alexander Saldanha

According to our database1, Alexander Saldanha authored at least 28 papers between 1988 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2007
FSM Encoding for BDD Representations.
Int. J. Appl. Math. Comput. Sci., 2007

2000
Timing Analysis with Implicitly Specified False Paths.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Functional timing optimization.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A methodology for correct-by-construction latency insensitive design.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Partial-scan delay fault testing of asynchronous circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

An Exact Input Encoding Algorithm for BDDs Representing FSMs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Symbolic two-level minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Approximate timing analysis of combinational circuits under the XBD0 model.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Trace driven logic synthesis - application to power minimization.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
Compact and complete test set generation for multiple stuck-faults.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Verification of Electronic Systems.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Delay fault coverage, test set size, and performance trade-offs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Functional clock schedule optimization.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Fast discrete function evaluation using decision diagrams.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool.
Proceedings of the 32st Conference on Design Automation, 1995

Supervisory Control of Finite State Machines.
Proceedings of the Computer Aided Verification, 1995

1994
Satisfaction of input and output encoding constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Circuit structure relations to redundancy and delay.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Performance Optimization Using Exact Sensitization.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Delay Fault Coverage and Performance Tradeoffs.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.
Proceedings of the 29th Design Automation Conference, 1992

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.
Proceedings of the 29th Design Automation Conference, 1992

1991
Is redundancy necessary to reduce delay?
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Framework for Satisfying Input and Output Encoding Constraints.
Proceedings of the 28th Design Automation Conference, 1991

1990
Timing Optimization with Testability Considerations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Multi-level Logic Simplification Using Don't Cares and Filters.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
PLA optimization using output encoding.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988


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