Aniruddha N. Udipi

According to our database, Aniruddha N. Udipi authored at least 10 papers between 2009 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems.

Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic, Parthasarathy Ranganathan

Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2014

Simulating DRAM controllers for future system architecture exploration.

Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas F. Wenisch, Aniruddha N. Udipi

Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

2013

Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device.

Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

Designing Efficient Memory for Future Computing Systems.

Aniruddha N. Udipi

PhD thesis, 2012

LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems.

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011

Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems.

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

Rethinking DRAM design and organization for energy-constrained multi-cores.

Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Towards scalable, energy-efficient, bus-based on-chip networks.

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian

Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

2009

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.

Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Non-uniform power access in large caches with low-swing wires.

Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian

Proceedings of the 16th International Conference on High Performance Computing, 2009