Ankit Kaul

Orcid: 0000-0003-0301-1349

According to our database1, Ankit Kaul authored at least 8 papers between 2020 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Methodologies for Modeling and Optimization of 2.5-D and 3-D Integration Architectures for Compute-In-Memory Applications.
PhD thesis, 2023

2022
A Compute-in-Memory Hardware Accelerator Design With Back-End-of-Line (BEOL) Transistor Based Reconfigurable Interconnect.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021
Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Electrical and Performance Benefits of Advanced Monolithic Cooling for 2.5D Heterogeneous ICs.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System Performance.
Proceedings of the IEEE International 3D Systems Integration Conference, 2021

2020
Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication.
Proceedings of the VLSI-SoC: Design Trends, 2020

A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020


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