Yoav Etsion

According to our database1, Yoav Etsion authored at least 52 papers between 2001 and 2019.

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Bibliography

2019
The TrieJax Architecture: Accelerating Graph Operations Through Relational Joins.
CoRR, 2019

Using SMT to accelerate nested virtualization.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Do-It-Yourself Virtual Memory Translation.
Operating Systems Review, 2018

Efficiently Charting RDF.
CoRR, 2018

Towards Memory Prefetching with Neural Networks: Challenges and Insights.
CoRR, 2018

Inter-thread Communication in Multithreaded, Reconfigurable Coarse-grain Arrays.
CoRR, 2018


Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Architectural Support for Unlimited Memory Versioning and Renaming.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Snapshot-Based Synchronization: A Fast Replacement for Hand-over-Hand Locking.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018


DATS - Data Containers for Web Applications.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Towards a Deterministic Fine-Grained Task Ordering Using Multi-Versioned Memory.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Do-It-Yourself Virtual Memory Translation.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

DFiant: A dataflow hardware description language.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC.
Proceedings of the Twelfth European Conference on Computer Systems, 2017

Flexible Caching in Trie Joins.
Proceedings of the 20th International Conference on Extending Database Technology, 2017

2016
Flexible Caching in Trie Joins.
CoRR, 2016

NeSC: Self-virtualizing nested storage controller.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2015
Control flow coalescing on a hybrid dataflow/von Neumann GPGPU.
Proceedings of the 48th International Symposium on Microarchitecture, 2015

Semantic locality and context-based prefetching using reinforcement learning.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014
Hybrid Dataflow/von-Neumann Architectures.
IEEE Trans. Parallel Distrib. Syst., 2014

Memristor-Based Multithreading.
Computer Architecture Letters, 2014

O-structures: semantics for versioned memory.
Proceedings of the workshop on Memory Systems Performance and Correctness, 2014

Loop-Aware Memory Prefetching Using Code Block Working Sets.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Single-graph multiple flows: Energy efficient design alternative for GPGPUs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

CODOMs: Protecting software with Code-centric memory Domains.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
Analysis of the Task Superscalar Architecture Hardware Design.
Proceedings of the International Conference on Computational Science, 2013

2012
Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling.
IEEE Trans. Computers, 2012

On the simulation of large-scale architectures using multiple application abstraction levels.
TACO, 2012

2011
Implementation of a hierarchical N-body simulator using the Ompss programming model.
Proceedings of the first workshop on Irregular applications: architectures and algorithm, 2011

Trace-driven simulation of multithreaded applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

On the memory system requirements of future scientific applications: Four case-studies.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Design and implementation of a generic resource sharing virtual time dispatcher.
Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, 2010

Interleaving granularity on high bandwidth memory architecture for CMPs.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Task Superscalar: An Out-of-Order Task Pipeline.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Can Manycores Support the Memory Requirements of Scientific Applications?
Proceedings of the Computer Architecture, 2010

2009
A global scheduling framework for virtualization environments.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2007
Backfilling Using System-Generated Predictions Rather than User Runtime Estimates.
IEEE Trans. Parallel Distrib. Syst., 2007

Fine-grain analysis of common coupling and its application to a Linux case study.
Journal of Systems and Software, 2007

Probabilistic Prediction of Temporal Locality.
Computer Architecture Letters, 2007

Secretly Monopolizing the CPU Without Superuser Privileges.
Proceedings of the 16th USENIX Security Symposium, Boston, MA, USA, August 6-10, 2007, 2007

Fine grained kernel logging with KLogger: experience and insights.
Proceedings of the 2007 EuroSys Conference, Lisbon, Portugal, March 21-23, 2007, 2007

L1 Cache Filtering Through Random Selection of Memory References.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Process prioritization using output production: Scheduling for multimedia.
TOMCCAP, 2006

2005
Modeling User Runtime Estimates.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2005

System noise, OS clock ticks, and fine-grained parallel applications.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

2004
Desktop scheduling: how can we know what the user wants?
Proceedings of the Network and Operating System Support for Digital Audio and Video, 2004

2003
Effects of clock resolution on the scheduling of interactive and soft real-time processes.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2003

2001
User-Level Communication in a System with Gang Scheduling.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001


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