Behnam Ghavami
Orcid: 0000-0001-5391-383X
According to our database1,
Behnam Ghavami
authored at least 66 papers
between 2007 and 2024.
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Bibliography
2024
Correction to: Using a privacy‑enhanced authentication process to secure IoT‑based smart grid infrastructures.
J. Supercomput., January, 2024
Using a privacy-enhanced authentication process to secure IoT-based smart grid infrastructures.
J. Supercomput., January, 2024
2023
CoRR, 2023
A Decision Making Approach for Chemotherapy Planning based on Evolutionary Processing.
CoRR, 2023
Unraveling the Integration of Deep Machine Learning in FPGA CAD Flow: A Concise Survey and Future Insights.
CoRR, 2023
scaleTRIM: Scalable TRuncation-Based Integer Approximate Multiplier with Linearization and Compensation.
CoRR, 2023
Proceedings of the 28th International Computer Conference, Computer Society of Iran, 2023
2022
A GPU-based accelerated ELM and deep-ELM training algorithms for traditional and deep neural networks classifiers.
Intell. Syst. Appl., 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
FitAct: Error Resilient Deep Neural Networks via Fine-Grained Post-Trainable Activation Functions.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
A Statistical Gate Sizing Method for Timing Yield and Lifetime Reliability Optimization of Integrated Circuits.
IEEE Trans. Emerg. Top. Comput., 2021
SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs.
CoRR, 2021
Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment.
IEEE Access, 2021
Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
2020
A smart adaptive particle swarm optimization-support vector machine: android botnet detection application.
J. Supercomput., 2020
Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects.
IEEE Trans. Circuits Syst., 2020
Improving Combinational Circuit Reliability Against Multiple Event Transients via a Partition and Restructuring Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
J. Supercomput., 2019
Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits.
IET Circuits Devices Syst., 2019
Comput. Electr. Eng., 2019
Soft Error Reliability Improvement of Digital Circuits by Exploiting a Fast Gate Sizing Scheme.
IEEE Access, 2019
2018
Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines.
J. Supercomput., 2018
IEEE Des. Test, 2018
2017
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing.
IEEE Trans. Reliab., 2017
Soft error tolerant design of combinational circuits based on a local logic substitution scheme.
Microelectron. J., 2017
Turkish J. Electr. Eng. Comput. Sci., 2017
Artif. Intell. Medicine, 2017
2016
A Metallic CNT Tolerant Design Methodology for Carbon Nanotube-Based Programmable Gate Arrays.
J. Circuits Syst. Comput., 2016
A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits.
J. Electron. Test., 2016
2015
Microelectron. Reliab., 2015
Soft error rate estimation of combinational circuits based on vulnerability analysis.
IET Comput. Digit. Tech., 2015
Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit.
ACM J. Emerg. Technol. Comput. Syst., 2013
2011
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors.
Des. Autom. Embed. Syst., 2011
Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits Using Independent N2-Transistor Structures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Timing yield estimation of carbon nanotube-based digital circuits in the presence of nanotube density variation and metallic-nanotubes.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Microelectron. J., 2010
An Efficient Energy Estimation Methodology for Quasi Delay Insensitive Template-Based Asynchronous Circuits.
J. Low Power Electron., 2010
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
2009
Comput. Electr. Eng., 2009
High performance asynchronous design flow using a novel static performance analysis method.
Comput. Electr. Eng., 2009
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Statistical static performance analysis of asynchronous circuits considering process variation.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor.
Proceedings of the IFIP VLSI-SoC 2007, 2007
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007