Bing J. Sheu

According to our database1, Bing J. Sheu authored at least 53 papers between 1987 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2002
An efficient parameter extraction method using statistical optimization in S-CMOS deep-submicron/nanometer model.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Panel: Is Nanometer Design Under Control?
Proceedings of the 38th Design Automation Conference, 2001

2000
Compact VLSI Neural Network Circuit with High-Capacity Dynamic Synapses.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1998
A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Advances in efficient optical links to enhance desktop multimedia processor systems.
IEEE Trans. Circuits Syst. Video Technol., 1997

Guest Editorial.
IEEE Trans. Circuits Syst. Video Technol., 1997

A CDMA communication detector with robust near-far resistance using paralleled array processors.
IEEE Trans. Circuits Syst. Video Technol., 1997

A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Optimal solutions for cellular neural networks by paralleled hardware annealing.
IEEE Trans. Neural Networks, 1996

VLSI design for real-time signal processing based on biologically realistic neural models.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

A neural network communication equalizer with optimized solution capability.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995
VLSI-Compatible Cellular Neural Networks with Optimal Solution Capability for Optimization.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

VLSI Neural Network Implementation of a Hippocampal Model.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

VLSI Design of Cellular Neutral Networks with Annealing and Optical Input Capabilities.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Constructing Intelligent Microsystems with Modular VLSI Networks Design.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A hippocampal model implementation using VLSI table-look-up and model-based approaches.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

A compact VLSI design for recursive neural networks with hardware annealing capability.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Smart-pixel array processors based on optimal cellular neural networks for space sensor applications.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

VLSI design of densely-connected array processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
Testing of programmable analog neural network chips.
J. VLSI Signal Process., 1994

VLSI systolic binary tree-searched vector quantizer for image compression.
IEEE Trans. Very Large Scale Integr. Syst., 1994

A Gaussian synapse circuit for analog VLSI neural networks.
IEEE Trans. Very Large Scale Integr. Syst., 1994

An adaptive vector quantizer based on the Gold-Washing method for image compression.
IEEE Trans. Circuits Syst. Video Technol., 1994

Image compression using self-organization networks.
IEEE Trans. Circuits Syst. Video Technol., 1994

BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An Analog MOS Model for Circuit Simulation and Benchmark Test Results.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Search of Optimal Solutions in Multi-Level Neural Networks.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
A mixed-signal VLSI competitive neuroprocessor for video motion detection.
J. VLSI Signal Process., 1993

A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture.
J. VLSI Signal Process., 1993

VLSI neuroprocessors for video motion detection.
IEEE Trans. Neural Networks, 1993

Paralleled hardware annealing for optimal solutions on electronic neural networks.
IEEE Trans. Neural Networks, 1993

A programmable analog VLSI neural network processor for communication receivers.
IEEE Trans. Neural Networks, 1993

1992
A VLSI neural processor for image data compression using self-organization networks.
IEEE Trans. Neural Networks, 1992

A mixed-signal VLSI neuroprocessor for image restoration.
IEEE Trans. Circuits Syst. Video Technol., 1992

Image Compression on a VLSI Neural-Based Vector Quantizer.
Inf. Process. Manag., 1992

Adaptive vector quantizer for image compression using self-organization approach.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

Design of a multiprocessor DSP chip for flexible information processing.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

An Adaptive High-Speed Lossy Data Compression.
Proceedings of the IEEE Data Compression Conference, 1992

1991
Modified Hopfield neural networks for retrieving the optimal solution.
IEEE Trans. Neural Networks, 1991

Testing of Analog Neural Array-Processor Chips.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

A GaAs Receiver Module for Optoelectronic Computing and Interconnection.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Real-time high-ratio image compression using adaptive VLSI neuroprocessors.
Proceedings of the 1991 International Conference on Acoustics, 1991

A VLSI neuroprocessor for real-time image flow computing.
Proceedings of the 1991 International Conference on Acoustics, 1991

A Neural Network Based VLSI Vector Quantizer for Real-Time Image Compression.
Proceedings of the IEEE Data Compression Conference, 1991

1990
VLSI image processor using analog programmable synapses and neurons.
Proceedings of the IJCNN 1990, 1990

Parallel digital image restoration using adaptive VLSI neural chips.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Real-time computing of optical flow using adaptive VLSI neuroprocessors.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Automatic layout generation for mixed analog-digital VLSI neural chips.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1988
Device and circuit simulation interface for an integrated VLSI design environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An MOS transistor charge model for VLSI design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An investigation on local minima of a Hopfield network for optimization circuits.
Proceedings of International Conference on Neural Networks (ICNN'88), 1988

1987
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987


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