Davide Pandini

According to our database1, Davide Pandini authored at least 38 papers between 1993 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
Design methodology for low-power embedded microprocessors.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Evaluating the impact of substrate on power integrity in industrial microcontrollers.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Exploiting body biasing for leakage reduction: A case study.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2011
A design methodology for the automatic sizing of standard-cell libraries.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Evaluating Static CMOS Complex Cells in Technology Mapping.
Proceedings of the ARCS 2011, 2011

SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels.
Proceedings of the ARCS 2011, 2011

2010
Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization.
J. Low Power Electronics, 2010

A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009
Clock-tree synthesis for low-EMI design.
J. Embedded Computing, 2009

Statistical static timing analysis: A survey.
Integr., 2009

Variability in Advanced Nanometer Technologies: Challenges and Solutions.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

EMC-aware design on a microcontroller for automotive applications.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Robust Design-for-Productization Practices for High Quality Automotive Products.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Computing and design for software and silicon manufacturing.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Clock Distribution Techniques for Low-EMI Design.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Why we need statistical static timing analysis.
Proceedings of the 25th International Conference on Computer Design, 2007

A Fully-Automated Desynchronization Flow for Synchronous Circuits.
Proceedings of the 44th Design Automation Conference, 2007

2006
Power Supply Selective Mapping for Accurate Timing Analysis.
J. Low Power Electronics, 2006

Spectral Analysis of the On-Chip Waveforms to Generate Guidelines for EMC-Aware Design.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

An ultra-low energy asynchronous processor for Wireless Sensor Networks.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
Including Power Supply Variations into Static Timing Analysis: Methodology and Flow.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A complete methodology for an accurate static noise analysis.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis.
Proceedings of the 2005 Design, 2005

2004
Design Methodologies and Architecture Solutions for High-Performance Interconnects.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

A comparison between mask- and field-programmable routing structures on industrial FPGA architectures.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Global and local congestion optimization in technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Bounding the efforts on congestion optimization for physical synthesis.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
Understanding and addressing the impact of wiring congestion during technology mapping.
Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion-Aware Logic Synthesis.
Proceedings of the 2002 Design, 2002

2000
Crosstalk Aware Static Timing Analysis: A Two Step Approach.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1998
Reduced Order Macromodel of Coupled Interconnects for Timing and Functional Verification of Sub Half-micron IC Designs.
Proceedings of the ASP-DAC '98, 1998

1995
Optimum CMOS stack generation with analog constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

1994
Simultaneous Placement and Module Optimization of Analog IC's.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Automatic Generation of Transistor Stacks for CMOS Analog Layout.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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