Roberto Zafalon

According to our database1, Roberto Zafalon authored at least 32 papers between 1998 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2013
Smart System Design: Industrial Challenges and Perspectives.
Proceedings of the 2013 IEEE 14th International Conference on Mobile Data Management, Milan, Italy, June 3-6, 2013, 2013

e-Mobility the next frontier for automotive industry.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Solid state photodetectors for nuclear medical imaging applications.
Proceedings of the Design, Automation and Test in Europe, 2011


2010

Panel: First commandment at least, do nothing well!
Proceedings of the Design, Automation and Test in Europe, 2010

2006
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electron., 2006

Low-power design tools: are EDA vendors taking this matter seriously?
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005

Reducing the complexity of instruction-level power models for VLIW processors.
Des. Autom. Embed. Syst., 2005

Energy-Aware System-on-Chip for 5 GHz Wireless LANs.
Proceedings of the Integrated Circuit and System Design, 2005

Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.
Proceedings of the Integrated Circuit and System Design, 2004

Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Analyzing On-Chip Communication in a MPSoC Environment.
Proceedings of the 2004 Design, 2004

System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip.
Proceedings of the 2004 Design, 2004

System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

Branch prediction techniques for low-power VLIW processors.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.
Proceedings of the 2003 Design, 2003

2002
Low-power data forwarding for VLIW embedded architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2002

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.
Des. Autom. Embed. Syst., 2002

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002

Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002

2001
Low-power technology mapping for mixed-swing logic.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Exploiting data forwarding to reduce the power budget of VLIW embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.
Proceedings of the Integrated Circuit Design, 2000

Power Macromodeling for a High Quality RT-Level Power Estimation.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1999
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning.
Proceedings of the 36th Conference on Design Automation, 1999

Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998
Power invariant vector compaction based on bit clustering and temporal partitioning.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Automatic characterization and modeling of power consumption in static RAMs.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998


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