Christopher Bengel

Orcid: 0000-0002-2892-9837

According to our database1, Christopher Bengel authored at least 18 papers between 2020 and 2024.

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Bibliography

2024
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Ternary Łukasiewicz logic using memristive devices.
Neuromorph. Comput. Eng., December, 2023

A Physical Description of the Variability in Single-ReRAM Devices and Hardware-Based Neuronal Networks.
Adv. Intell. Syst., November, 2023

Bit slicing approaches for variability aware ReRAM CIM macros.
it Inf. Technol., May, 2023

Devices and Architectures for Efficient Computing In-Memory (CIM) Design.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory Computing.
Proceedings of the IEEE International Memory Workshop, 2023

Realization of Ternary Łukasiewicz Logic using BiFeO3-based Memristive Devices.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Reliability aspects of binary vector-matrix-multiplications using ReRAM devices.
Neuromorph. Comput. Eng., 2022

MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory.
ACM J. Emerg. Technol. Comput. Syst., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Realization of Memristor-aided Logic Gates with Analog Memristive Devices.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

A failure analysis framework of ReRAM In-Memory Logic operations.
Proceedings of the IEEE International Test Conference in Asia, 2022

Experimental and Theoretical Analysis of Stateful Logic in Passive and Active Crossbar Arrays for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Analysis of VMM Operations on 1S1R Crossbar Arrays and the Influence of Wire Resistances.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


2021
Implementation of Multinary Łukasiewicz Logic Using Memristive Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Variability-Aware Modeling of Filamentary Oxide-Based Bipolar Resistive Switching Cells Using SPICE Level Compact Models.
IEEE Trans. Circuits Syst., 2020


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