Chao Wang

Orcid: 0000-0003-4836-7648

Affiliations:
  • Beihang University, School of Electronics and Information Engineering, Beijing, China


According to our database1, Chao Wang authored at least 17 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2025

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025

Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range.
Proceedings of the 14th International Conference on Modern Circuits and Systems Technologies, 2025

Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode.
Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Process and Design Considerations for Spin Orbit Torque MRAM.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023
Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

A Robust Time-based Error-Proofing Readout Scheme for MRAM.
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

2022
Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Parallel Computing in Memory Paradigm based on Reconfigurable Spin-Orbit Torque.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022

2021
Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories.
IEEE Trans. Circuits Syst., 2020

Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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