Matthias Hartmann

According to our database1, Matthias Hartmann authored at least 43 papers between 2007 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Tracking the Continuous Dynamics of Numerical Processing: A Brief Review and Editorial.
JNC, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Non-musicians also have a piano in the head: evidence for spatial-musical associations from line bisection tracking.
Cognitive Processing, 2017

2016
Eye Movements Reveal Mental Looking Through Time.
Cognitive Science, 2016

Routing optimization for IP networks with loop-free alternates.
Computer Networks, 2016

2015
Optimization and design of network architectures for future internet routing.
PhD thesis, 2015

2014
POCO-framework for Pareto-optimal resilient controller placement in SDN-based core networks.
Proceedings of the 2014 IEEE Network Operations and Management Symposium, 2014

POCO-PLC: Enabling dynamic pareto-optimal resilient controller placement in SDN networks.
Proceedings of the 2014 Proceedings IEEE INFOCOM Workshops, Toronto, ON, Canada, April 27, 2014

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Feasibility exploration of NVM based I-cache through MSHR enhancements.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Comparison of IP-based and explicit paths for one-to-one fast reroute in MPLS networks.
Telecommunication Systems, 2013

Crowdsourcing and its Impact on Future Internet Usage.
it - Information Technology, 2013

Big Data.
Informatik Spektrum, 2013

Global Locator, Local Locator, and Identifier Split (GLI-Split).
Future Internet, 2013

A Survey of Mapping Systems for Locator/Identifier Split Internet Routing.
IEEE Communications Surveys and Tutorials, 2013

Pareto-optimal resilient controller placement in SDN-based core networks.
Proceedings of the 25th International Teletraffic Congress, 2013

Using Optimized Virtual Network Embedding for Network Dimensioning.
Proceedings of the 2013 Conference on Networked Systems, 2013

Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Early exploration for platform architecture instantiation with multi-mode application partitioning.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Self-motion perception influences number processing: evidence from a parity task.
Cognitive Processing, 2012

Algorithm-Architecture Co-Optimization of Area-Efficient SDR Baseband for Highly Diversified Digital TV Standards.
Proceedings of the 75th IEEE Vehicular Technology Conference, 2012

Integration of LISP and LISP-MN into INET.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

Parameters and challenges for Virtual Network embedding in the Future Internet.
Proceedings of the 2012 IEEE Network Operations and Management Symposium, 2012

2011
ResiLyzer: Ein Werkzeug zur Analyse der Ausfallsicherheit in paketvermittelten Kommunikationsnetzen.
Praxis der Informationsverarbeitung und Kommunikation, 2011

A multi-threaded coarse-grained array processor for wireless baseband.
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011

Overview of a Software Defined Downlink Inner Receiver for Category-E LTE-Advanced UE.
Proceedings of IEEE International Conference on Communications, 2011

Loop-free convergence using ordered FIB updates: Analysis and routing optimization.
Proceedings of the 8th International Workshop on the Design of Reliable Communication Networks, 2011

2010
Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Signal Processing Systems, 2010

FIRMS: A Mapping System for Future Internet Routing.
IEEE Journal on Selected Areas in Communications, 2010

Communication Networks Efficiency of routing and resilience mechanisms in packet-switched communication networks.
European Transactions on Telecommunications, 2010

Belehrung im elektronischen Fernabsatz.
Computer und Recht, 2010

Loop-free alternates and not-via addresses: A proper combination for IP fast reroute?
Computer Networks, 2010

Improvements to LISP Mobile Node.
Proceedings of the 22nd International Teletraffic Congress, 2010

Optimizing unique shortest paths for resilient routing and fast reroute in IP-based networks.
Proceedings of the IEEE/IFIP Network Operations and Management Symposium, 2010

ResiLyzer: A Tool for Resilience Analysis in Packet-Switched Communication Networks.
Proceedings of the Measurement, 2010

Effectiveness of Link Cost Optimization for IP Rerouting and IP Fast Reroute.
Proceedings of the Measurement, 2010

2009
Relaxed multiple routing configurations: IP fast reroute for single and correlated failures.
IEEE Trans. Network and Service Management, 2009

Threshold configuration and routing optimization for PCN-based resilient admission control.
Computer Networks, 2009

2008
Future Internet Routing: Motivation and Design Issues (Routing im Internet der Zukunft: Hintergründe und Gestaltungsansätze).
it - Information Technology, 2008

Relaxed multiple routing configurations for IP fast reroute.
Proceedings of the IEEE/IFIP Network Operations and Management Symposium: Pervasive Management for Ubioquitous Networks and Services, 2008

Predictors of metabolic energy expenditure from body acceleration and mechanical energies in new generation active computer games.
Proceedings of the Computer Science in Sport - Mission and Methods, 07.09. - 10.09.2008, 2008

2007
Robust IP Link Costs for Multilayer Resilience.
Proceedings of the NETWORKING 2007. Ad Hoc and Sensor Networks, 2007

Still Image Processing on Coarse-Grained Reconfigurable Array Architectures.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007


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