Pei-Wen Luo

According to our database, Pei-Wen Luo authored at least 16 papers between 2008 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors.

Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.

Hui Geng, Jianming Liu, Jinglan Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi

Integr., 2016

2015

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs.

Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo

ACM Trans. Design Autom. Electr. Syst., 2015

Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.

Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.

Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu

Proceedings of the Symposium on VLSI Circuits, 2015

2014

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.

Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Variation aware optimal threshold voltage computation for on-chip noise sensors.

Tao Wang, Chun Zhang, Jinjun Xiong, Pei-Wen Luo, Liang-Chia Cheng, Yiyu Shi

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits.

Chien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo

ACM Trans. Design Autom. Electr. Syst., 2013

Benchmarking for research in power delivery networks of three-dimensional integrated circuits.

Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi

Proceedings of the International Symposium on Physical Design, 2013

2012

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).

Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.

Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.

Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Yield-award placement optimization for Switched-Capacitor analog integrated circuits.

Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

2010

Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.

Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Yield evaluation of analog placement with arbitrary capacitor ratio.

Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.

Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008