Daniel Ziener

Orcid: 0000-0001-6449-9208

Affiliations:
  • University of Erlangen-Nuremberg, Germany


According to our database1, Daniel Ziener authored at least 46 papers between 2006 and 2022.

Collaborative distances:

Timeline

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Bibliography

2022
Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs.
Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022

2021
An Energy-Efficient FPGA-based Convolutional Neural Network Implementation.
Proceedings of the 29th Signal Processing and Communications Applications Conference, 2021

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
A Complete Open Source Design Flow for Gowin FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Throughput optimizations for FPGA-based deep neural network inference.
Microprocess. Microsystems, 2018

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems.
CoRR, 2018

Configuration Tampering of BRAM-based AES Implementations on FPGAs.
Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems
PhD thesis, 2017

Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning.
Integr., 2017

2016
FPGA-Based Dynamically Reconfigurable SQL Query Processing.
ACM Trans. Reconfigurable Technol. Syst., 2016

Efficient deep neural network acceleration through FPGA-based batch processing.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A LUT-Based Approximate Adder.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

FPGA Versus Software Programming: Why, When, and How?
Proceedings of the FPGAs for Software Programmers, 2016

2015
Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015).
CoRR, 2015

A co-design approach for accelerated SQL query processing via FPGA-based data filtering.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014).
CoRR, 2014

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Symbolic system-level design methodology for multi-mode reconfigurable systems.
Des. Autom. Embed. Syst., 2013

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN).
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Partial Reconfiguration on FPGAs in Practice - Tools and Applications.
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

2011
An FPGA implementation of a threat-based strategy for Connect6.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Runtime stress-aware replica placement on reconfigurable devices under safety constraints.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Stress-Aware Module Placement on Reconfigurable Devices.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Symbolic design space exploration for multi-mode reconfigurable systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs.
PhD thesis, 2010

Multiplexing Methods for Power Watermarking.
Proceedings of the HOST 2010, 2010

Using the Power Side Channel of FPGAs for Communication.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

A rapid prototyping system for error-resilient multi-processor systems-on-chip.
Proceedings of the Design, Automation and Test in Europe, 2010

New Directions for IP Core Watermarking and Identification.
Proceedings of the Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

2009
Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs.
Int. J. Auton. Adapt. Commun. Syst., 2009

2008
Power Signature Watermarking of IP Cores for FPGAs.
J. Signal Process. Syst., 2008

Netlist-level IP protection by watermarking for LUT-based FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Concepts for Autonomous Control Flow Checking for Embedded CPUs.
Proceedings of the Autonomic and Trusted Computing, 5th International Conference, 2008

2006
FPGA core watermarking based on power signature analysis.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006


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