Matthew Cotter

According to our database1, Matthew Cotter authored at least 18 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




A Practitioner's Guide to Optimizing the Interactions Between Modelers and Domain Experts.
Proceedings of the 2019 IEEE International Systems Conference, 2019

SysML executable systems of system architecture definition: A working example.
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Enabling New Computation Paradigms with HyperFET - An Emerging Device.
IEEE Trans. Multi Scale Comput. Syst., 2016

Exploring architectural heterogeneity in intelligent vision systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Visual co-occurrence network: using context for large-scale object recognition in retail.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Image Segmentation Using Frequency Locking of Coupled Oscillators.
CoRR, 2014

Understanding the landscape of accelerators for vision.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Computational Architectures Based on Coupled Oscillators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A hardware accelerated multilevel visual classifier for embedded visual-assist systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Neuro Inspired Computing with Coupled Relaxation Oscillators.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Hardware Acceleration for Neuromorphic Vision Algorithms.
J. Signal Process. Syst., 2013

Design of energy-efficient circuits and systems using tunnel field effect transistors.
IET Circuits Devices Syst., 2013

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications.
Proceedings of the International Symposium on Quality Electronic Design, 2013

System-On-Chip for Biologically Inspired Vision Applications.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

Ultra Low Power Circuit Design Using Tunnel FETs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Accelerating neuromorphic vision algorithms for recognition.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A framework for accelerating neuromorphic-vision algorithms on FPGAs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

FPGA-accelerator system for computing biologically inspired feature extraction models.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011