David Boland

According to our database, David Boland authored at least 49 papers between 2008 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

S$^{3}$CA: A Sparse Strip Spectral Correlation Analyzer.

Carol Jingyi Li, Richard Rademacher, David Boland, Craig T. Jin, Chad M. Spooner, Philip H. W. Leong

IEEE Signal Process. Lett., 2024

2023

fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library.

Binglei Lou, David Boland, Philip H. W. Leong

ACM Trans. Reconfigurable Technol. Syst., September, 2023

Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis.

Carol Jingyi Li, Xiangwei Li, Binglei Lou, Craig T. Jin, David Boland, Philip H. W. Leong

ACM Trans. Reconfigurable Technol. Syst., September, 2023

A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation.

Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland

ACM Trans. Reconfigurable Technol. Syst., March, 2023

On-Board Federated Learning in Orbital Edge Computing.

Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler

Proceedings of the 29th IEEE International Conference on Parallel and Distributed Systems, 2023

BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning.

Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration.

Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Single-Batch CNN Training using Block Minifloats on FPGAs.

Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022

Rethinking Embedded Blocks for Machine Learning Applications.

Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland

ACM Trans. Reconfigurable Technol. Syst., 2022

FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic.

Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

A Block Minifloat Representation for Training Deep Neural Networks.

Sean Fox, Seyedramin Rasoulinezhad, Julian Faraone, David Boland, Philip H. W. Leong

Proceedings of the 9th International Conference on Learning Representations, 2021

MLBlocks: FPGA Blocks for Machine Learning Applications.

Seyedramin Rasoulinezhad, David Boland, Philip H. W. Leong

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers.

Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong

IEEE Trans. Very Large Scale Integr. Syst., 2020

Derivation of Respiratory Metrics in Health and Asthma.

Joseph Prinable, Peter Jones, David Boland, Alistair Lee McEwan, Cindy Thamrin

Sensors, 2020

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations.

Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

CoRR, 2020

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency.

Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

CoRR, 2020

Real-time Automatic Modulation Classification using RFSoC.

Stephen Tridgell, David Boland, Philip H. W. Leong, Ryan Kastner, Alireza Khodamoradi, Siddhartha

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations.

Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

A Two-Speed, Radix-4, Serial-Parallel Multiplier.

Duncan J. M. Moss, David Boland, Philip H. W. Leong

IEEE Trans. Very Large Scale Integr. Syst., 2019

Unrolling Ternary Neural Networks.

Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong

ACM Trans. Reconfigurable Technol. Syst., 2019

Real-Time Automatic Modulation Classification.

Stephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha

Proceedings of the International Conference on Field-Programmable Technology, 2019

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency.

Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2019

Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs.

Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation.

Siddhartha, Yee Hui Lee, Duncan J. M. Moss, Julian Faraone, Perry Blackmore, Daniel Salmond, David Boland, Philip H. W. Leong

Proceedings of the 2018 IEEE Military Communications Conference, 2018

Real-time FPGA-based Anomaly Detection for Radio Frequency Signals.

Duncan J. M. Moss, David Boland, Peyam Pourbeik, Philip Heng Wai Leong

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques.

Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2018

Customizing Low-Precision Deep Neural Networks for FPGAs.

Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method.

Sean Fox, David Boland, Philip Heng Wai Leong

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

FPGA-based layered/enhanced ACO-OFDM transmitter.

Qibing Wang, Binhuang Song, Bill Corcoran, David Boland, Leimeng Zhuang, Yiwei Xie, Arthur James Lowery

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

FPGA acceleration of multilevel ORB feature extraction for computer vision.

Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Dynamic bitwidth assignment for efficient dot products.

Simon Joel Schmidt, David Boland

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination.

David Boland

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015

Imprecise Datapath Design: An Overclocking Approach.

Kan Shi, David Boland, George A. Constantinides

ACM Trans. Reconfigurable Technol. Syst., 2015

2014

Efficient FPGA implementation of digit parallel online arithmetic operators.

Kan Shi, David Boland, George A. Constantinides

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.

Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

A Scalable Precision Analysis Framework.

David Boland, George A. Constantinides

IEEE Trans. Multim., 2013

Overclocking datapath for latency-error tradeoff.

Kan Shi, David Boland, George A. Constantinides

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation.

David Boland, George A. Constantinides

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Word-length optimization beyond straight line code.

David Boland, George A. Constantinides

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Accuracy-Performance Tradeoffs on an FPGA through Overclocking.

Kan Shi, David Boland, George A. Constantinides

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012

Precision analysis for hardware acceleration of numerical algorithms.

David Boland

PhD thesis, 2012

A scalable approach for automated precision analysis.

David Boland, George A. Constantinides

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.

Xuan You Tan, David Boland, George A. Constantinides

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods.

David Boland, George A. Constantinides

ACM Trans. Reconfigurable Technol. Syst., 2011

Bounding Variable Values and Round-Off Effects Using Handelman Representations.

David Boland, George A. Constantinides

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA.

Christophe Le Lann, David Boland, George A. Constantinides

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

Automated Precision Analysis: A Polynomial Algebraic Approach.

David Boland, George A. Constantinides

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.

David Boland, George A. Constantinides

Proceedings of the Reconfigurable Computing: Architectures, 2010

2008

An FPGA-based implementation of the MINRES algorithm.

David Boland, George A. Constantinides

Proceedings of the FPL 2008, 2008