Fabien Chaix

According to our database1, Fabien Chaix authored at least 22 papers between 2010 and 2024.

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Bibliography

2024
MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack.
CoRR, 2023

2022
Optimized Page Fault Handling During RDMA.
IEEE Trans. Parallel Distributed Syst., 2022

2020
PART: Pinning Avoidance in RDMA Technologies.
Proceedings of the 14th IEEE/ACM International Symposium on Networks-on-Chip, 2020

2019
Implementation and Impact of an Ultra-Compact Multi-FPGA Board for Large System Prototyping.
Proceedings of the 2019 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2019

Towards Exascale: Measuring the Energy Footprint of Astrophysics HPC Simulations.
Proceedings of the 15th International Conference on eScience, 2019

2017
A Case for Uni-directional Network Topologies in Large-Scale Clusters.
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017

2016
Optical network technologies for HPC: computer-architects point of view.
IEICE Electron. Express, 2016

Suitability of the Random Topology for HPC Applications.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Analysis of Adaptive Mapping of Parallelized Application on Multicore System.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016


2015
A Systematic Evaluation of Emerging Mesh-like CMP NoCs.
Proceedings of the Eleventh ACM/IEEE Symposium on Architectures for networking and communications systems, 2015

2014
Congestion-Aware Adaptive Routing in 2D-Mesh Multicores.
Proceedings of the 2014 IEEE 13th International Symposium on Network Computing and Applications, 2014

Layout-aware expandable low-degree topology.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Darkfiber Planning for Extensible HPC Network Design under Uncertainties.
Proceedings of the Second International Symposium on Computing and Networking, 2014

A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Variability-aware and fault-tolerant self-adaptive applications for many-core chips.
Proceedings of the 18th IEEE European Test Symposium, 2013

2011
Self-Recovering Parallel Applications in Multi-core Systems.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

Variability-aware task mapping strategies for many-cores processor chips.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A fault-tolerant deadlock-free adaptive routing for on chip interconnects.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems.
Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010


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