Denis Dutoit

Orcid: 0000-0001-7786-0947

According to our database1, Denis Dutoit authored at least 18 papers between 2006 and 2021.

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Bibliography

2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.
Proceedings of the Euromicro Conference on Digital System Design, 2017

2016
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.
IEEE Des. Test, 2016

2015
3D advanced integration technology for heterogeneous systems.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
EUROSERVER: Energy Efficient Node for European Micro-Servers.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
3D stacking for multi-core architectures: From WIDEIO to distributed caches.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

3D integration for power-efficient computing.
Proceedings of the Design, Automation and Test in Europe, 2013

System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
3D NoC using through silicon Via: An asynchronous implementation.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip.
Proceedings of the NOCS 2011, 2011

3D Embedded multi-core: Some perspectives.
Proceedings of the Design, Automation and Test in Europe, 2011

Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2006
A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM.
IEEE J. Solid State Circuits, 2006


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