George English

According to our database, George English authored at least 4 papers between 2007 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2015

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban

IEEE J. Solid State Circuits, 2015

2014

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8^TM microprocessor.

Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2008

A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI.

Alexander V. Rylyakov, José A. Tierno, George English, Michael A. Sperling, Daniel J. Friedman

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI.

Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007