Anne E. Gattiker

According to our database1, Anne E. Gattiker authored at least 44 papers between 1994 and 2019.

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Bibliography

2019
Accelerating Conversational Agents Built With Off-the-Shelf Modularized Services.
IEEE Pervasive Comput., 2019

Video-Text Compliance: Activity Verification Based on Natural Language Instructions.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

2018
SimplerVoice: A Key Message & Visual Description Generator System for Illiteracy.
CoRR, 2018

2017
SCI-FII: Speculative Conversational Interface Framework for Incremental Inference on Modularized Services.
Proceedings of the 18th IEEE International Conference on Mobile Data Management, 2017

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

2014
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
IEEE J. Solid State Circuits, 2014

Unstructured text: Test analysis techniques applied to non-test problems.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Big data and test.
Proceedings of the 2014 International Test Conference, 2014

2013
Big Data text-oriented benchmark creation for Hadoop.
IBM J. Res. Dev., 2013


Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo.
Proceedings of the International Conference on Computational Science, 2013

2012
Guest Editors' Introduction: Yield Learning Processes and Methods.
IEEE Des. Test Comput., 2012

An oscillation-based test structure for timing information extraction.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011
Efficient and product-representative timing model validation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Invited paper: Yin and Yang of embedded sensors for post-scaling-era.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Using well/substrate bias manipulation to enhance voltage-test-based defect detection.
Proceedings of the 2011 IEEE International Test Conference, 2011

Post-Silicon Timing Validation Method Using Path Delay Measurements.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
System-level impact of chip-level failure mechanisms and screens.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2008
Unraveling Variability for Process/Product Improvement.
Proceedings of the 2008 IEEE International Test Conference, 2008

Using test data to improve IC quality and yield.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Guest Editor's Introduction: Getting More Out of Test.
IEEE Des. Test Comput., 2007

2006
High-performance CMOS variability in the 65-nm regime and beyond.
IBM J. Res. Dev., 2006

Getting More out of ITC.
IEEE Des. Test Comput., 2006

Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment.
Proceedings of the 2006 IEEE International Test Conference, 2006

IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2004
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Diagnosis Meets Physical Failure Analysis: How Long can we Succeed?
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Power supply transient signal analysis for defect-oriented test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Deformations of IC Structure in Test and Yield Learning.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Modeling the Economics of Testing: A DFT Perspective.
IEEE Des. Test Comput., 2002

Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Test structures for delay variability.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Static timing analysis based circuit-limited-yield estimation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Detecting delay faults using power supply transient signal analysis.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Timing Yield Estimation from Static Timing Analysis.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

2000
Test method evaluation experiments and data.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998
Toward understanding "Iddq-only" fails.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Current signatures: application [to CMOS].
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Smart Substrate MCMs.
J. Electron. Test., 1997

To DFT or Not to DFT?
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Current Signatures: Application.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Current signatures [VLSI circuit testing].
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1994
Smart-Substrate Multichip-Module Systems.
IEEE Des. Test Comput., 1994

Feasibility Study of Smart Substrate Multichip Modules.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994


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