Eric Fluhr

According to our database1, Eric Fluhr authored at least 20 papers between 2006 and 2018.

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Bibliography

2018
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4.
IEEE J. Solid State Circuits, 2018

IBM POWER9 circuit design and energy optimization for 14-nm technology.
IBM J. Res. Dev., 2018

2017
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Session 8 overview: Low-power digital circuits.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.
IEEE J. Solid State Circuits, 2015

IBM POWER8 circuit design and energy optimization.
IBM J. Res. Dev., 2015

Physical design and implementation of POWER8™ (P8) server class processor.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
F3: Adaptive design techniques for energy efficiency.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

POWER8 design methodology innovations for improving productivity and reducing power.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Session 3 overview: Processors.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2008
Design and Implementation of the POWER6 Microprocessor.
IEEE J. Solid State Circuits, 2008

2007
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.
IBM J. Res. Dev., 2007


2006
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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