Giuliano Sisto

According to our database, Giuliano Sisto authored at least 7 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs.

Mohamed Naeim, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic

Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.

Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert

IEEE Trans. Very Large Scale Integr. Syst., 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper.

Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne

Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, 2022

2021

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited).

Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

2019

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.

Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019