Anabela Veloso

According to our database, Anabela Veloso authored at least 16 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.

S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs.

Wen-Chieh Chen, S.-H. Chen, Anabela Veloso, Kateryna Serbulova, Geert Hellings, Guido Groeseneken

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.

Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling.

Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, Rongmei Chen, Anne Jourdain, N. Horiguchi

Proceedings of the International Conference on IC Design and Technology, 2022

2021

Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices.

Carlos H. S. Coelho, João Antonio Martino, Marcello Bellodi, Eddy Simoen, Anabela Veloso, Paula Ghedini Der Agopian

Microelectron. J., 2021

2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.

Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors.

Eddy Simoen, Alberto Vinicius Oliveira, Anabela Veloso, Adrian Vaisman Chasin, Romain Ritzenthaler, Hans Mertens, Naoto Horiguchi, Cor Claeys

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Scaling CMOS beyond Si FinFET: an analog/RF perspective.

Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2016

Beyond-Si materials and devices for more Moore and more than Moore applications.

Nadine Collaert, AliReza Alian, Hiroaki Arimura, Geert Boccardi, Geert Eneman, Jacopo Franco, Tsvetan Ivanov, Dennis Lin, Jérôme Mitard, S. Ramesh, R. Rooyackers, Marc Schaekers, A. Sibaya-Hernandez, S. Sioncke, Quentin Smets, Abhitosh Vais, A. Vandooren, Anabela Veloso, Anne S. Verhulst, Devin Verreck, Niamh Waldron, Amey Walke, Liesbeth Witters, H. Yu, X. Zhou, Aaron Voon-Yew Thean

Proceedings of the International Conference on IC Design and Technology, 2016

2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq

Proceedings of the 44th European Solid State Device Research Conference, 2014

2012

On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs.

Eddy Simoen, Marc Aoulaiche, Anabela Veloso, M. Jurczak, Cor Claeys, L. Mendes Almeida, Maria Glória Caño de Andrade, A. Luque Rodriguez, J. A. Jimenez Tejada, Christian Caillat, Pierre Fazan

Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2007

NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase.

A. Shickova, Ben Kaczer, Anabela Veloso, Marc Aoulaiche, M. Houssa, Herman E. Maes, Guido Groeseneken, J. A. Kittl

Microelectron. Reliab., 2007

Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V V_t Ni-FUSI CMOS transistors.

A. Rothschild, R. Mitsuhashi, Christoph Kerner, X. Shi, J. L. Everaert, L. Date, Thierry Conard, Olivier Richard, C. Vrancken, R. Verbeeck, Anabela Veloso, A. Lauwers, Muriel de Potter de ten Broeck, I. Debusschere, M. Jurczak, M. Niwa, Philippe Absil, S. Biesemans

Microelectron. Reliab., 2007

Reliability screening of high-k dielectrics based on voltage ramp stress.

A. Kerber, Luigi Pantisano, Anabela Veloso, Guido Groeseneken, Martin Kerber

Microelectron. Reliab., 2007