Gioele Mirabelli

Orcid: 0000-0001-7060-4836

According to our database1, Gioele Mirabelli authored at least 6 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

The Promise of 2-D Materials for Scaled Digital and Analog Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design enablement of CFET devices for sub-2nm CMOS nodes.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2017
Impact of impurities, interface traps and contacts on MoS2 MOSFETs: Modelling and experiments.
Proceedings of the 47th European Solid-State Device Research Conference, 2017


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