Liyang Pan

According to our database1, Liyang Pan authored at least 23 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An Energy-Efficient Gain-Cell Embedded DRAM Design with Weight Encoding for CNN Applications.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023

2019
OCStore: Accelerating Distributed Object Storage with Open-Channel SSDs.
Proceedings of the 39th IEEE International Conference on Distributed Computing Systems, 2019

2016
LSB page refresh based retention error recovery scheme for MLC NAND Flash.
Sci. China Inf. Sci., 2016

Fabrication of ultra-thin silicon chips using thermally decomposable temporary bonding adhesive.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

2015
A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time.
Sci. China Inf. Sci., 2015

Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT: PSS/Ta memristor.
Proceedings of the 15th Non-Volatile Memory Technology Symposium, 2015

Software Hardware Co-design for Side-Channel Analysis Platform on Security Chips.
Proceedings of the 11th International Conference on Computational Intelligence and Security, 2015

Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Air-gap/SiO2 liner TSVs with improved electrical performance.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Assessment methodology of the lateral migration component in data retention of 3D SONOS memories.
Microelectron. Reliab., 2014

Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology.
Sci. China Inf. Sci., 2014

An ultra-low-power extended counting ADC For large scale sensor arrays.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2011
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect.
J. Electron. Test., 2011

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect.
J. Electron. Test., 2011

A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
A novel high-speed and low-power negative voltage level shifter for low voltage applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC <i>nor</i> Flash Memories.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Embedded high-speed BCH decoder for new-generation NOR flash memories.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Pure logic CMOS based embedded Non-Volatile Random Access Memory for low power RFID application.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006
180nm 4Mb High Speed High Reliability Embedded SONOS Flash Memory.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


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