Imran Wali

According to our database, Imran Wali authored at least 9 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation.

Imran Wali, Alfonso Sánchez-Macián, Alexis Ramos, Juan Antonio Maestro

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2017

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.

Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda

J. Electron. Test., 2017

Towards approximation during test of Integrated Circuits.

Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

An efficient framework for design and assessment of arithmetic operators with Reduced-Precision Redundancy.

Imran Wali, Emmanuel Casseau, Arnaud Tisserand

Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

2016

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores.

Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda

J. Electron. Test., 2016

A low-cost susceptibility analysis methodology to selectively harden logic circuits.

Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture.

Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

An effective hybrid fault-tolerant architecture for pipelined cores.

Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults.

Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014