Mario Barbareschi

According to our database1, Mario Barbareschi
  • authored at least 41 papers between 2013 and 2018.
  • has a "Dijkstra number"2 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2018
An IP Core Remote Anonymous Activation Protocol.
IEEE Trans. Emerging Topics Comput., 2018

A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions.
IEEE Trans. on Circuits and Systems, 2018

Estimating dynamic power consumption for memristor-based CiM architecture.
Microelectronics Reliability, 2018

A PUF-based hardware mutual authentication protocol.
J. Parallel Distrib. Comput., 2018

Testing approximate digital circuits: Challenges and opportunities.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Synthesis of Finite State Machines on Memristor Crossbars.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

2017
Designing an SRAM PUF-based secret extractor for resource-constrained devices.
IJES, 2017

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices.
IJES, 2017

Approximate computing: Design & test for integrated circuits.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

A Proposal for the Secure Activation and Licensing of FPGA IP Cores.
Proceedings of the First Italian Conference on Cybersecurity (ITASEC17), 2017

Towards digital circuit approximation by exploiting fault simulation.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Memristive devices: Technology, design automation and computing frontiers.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Towards approximation during test of Integrated Circuits.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Formal Design Space Exploration for memristor-based crossbar architecture.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
Ring oscillators analysis for security purposes in Spartan-6 FPGAs.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.
JETC, 2016

XbarGen: A memristor based boolean logic synthesis tool.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Adopting Decision Tree Based Policy Enforcement Mechanism to Protect Reconfigurable Devices.
Proceedings of the Intelligent Interactive Multimedia Systems and Services 2016, 2016

How to Manage Keys and Reconfiguration in WSNs Exploiting SRAM Based PUFs.
Proceedings of the Intelligent Interactive Multimedia Systems and Services 2016, 2016

An extendible design exploration tool for supporting approximate computing techniques.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Partial FPGA bitstream encryption enabling hardware DRM in mobile environments.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Automatic Design Space Exploration of Approximate Algorithms for Big Data Applications.
Proceedings of the 30th International Conference on Advanced Information Networking and Applications Workshops, 2016

Implementing Hardware Decision Tree Prediction: A Scalable Approach.
Proceedings of the 30th International Conference on Advanced Information Networking and Applications Workshops, 2016

Chain-of-Trust for Microcontrollers using SRAM PUFs: the Linux Case Study.
Proceedings of the Advances on P2P, 2016

2015
Malicious traffic analysis on mobile devices: a hardware solution.
IJBDI, 2015

Decision Tree-Based Multiple Classifier Systems: An FPGA Perspective.
Proceedings of the Multiple Classifier Systems - 12th International Workshop, 2015

Digital Right Management for IP Protection.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Testing 90 nm microcontroller SRAM PUF quality.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Supply voltage variation impact on Anderson PUF quality.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A Cloud Based Architecture for Massive Sensor Data Analysis in Health Monitoring Systems.
Proceedings of the 10th International Conference on P2P, 2015

Authenticating IoT Devices with Physically Unclonable Functions Models.
Proceedings of the 10th International Conference on P2P, 2015

2014
Secure distribution infrastructure for hardware digital contents.
IET Computers & Digital Techniques, 2014

A hardware accelerator for data classification within the sensing infrastructure.
Proceedings of the 15th IEEE International Conference on Information Reuse and Integration, 2014

Advancing WSN physical security adopting TPM-based architectures.
Proceedings of the 15th IEEE International Conference on Information Reuse and Integration, 2014

Mobile Traffic Analysis Exploiting a Cloud Infrastructure and Hardware Accelerators.
Proceedings of the 2014 Ninth International Conference on P2P, 2014

2013
An FPGA-Based Smart Classifier for Decision Support Systems.
Proceedings of the Intelligent Distributed Computing VII, 2013

Network Traffic Analysis Using Android on a Hybrid Computing Architecture.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

Towards Automatic Generation of Hardware Classifiers.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

On the Adoption of FPGA for Protecting Cyber Physical Infrastructures.
Proceedings of the Eighth International Conference on P2P, 2013


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