Ivan Fabiano
According to our database1,
Ivan Fabiano
authored at least 10 papers
between 2013 and 2025.
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Bibliography
2025
A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz.
IEEE J. Solid State Circuits, April, 2025
An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process.
IEEE J. Solid State Circuits, April, 2025
A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical Driver and Chip-to-Module Long Reach Capability of 40dB in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2019
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2017
A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence.
IEEE J. Solid State Circuits, 2017
2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 1.7-2.1GHz +23dBm TX power compatible blocker tolerant FDD receiver with integrated duplexer in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2013
IEEE J. Solid State Circuits, 2013