Jean-Christophe Le Lann
Orcid: 0000-0003-2555-1805Affiliations:
- ENSTA Bretagne, Brest, France
According to our database1,
Jean-Christophe Le Lann
authored at least 21 papers
between 2001 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on twitter.com
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on orcid.org
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on jcll.fr
On csauthors.net:
Bibliography
2024
2023
Detection of AIS messages falsifications and spoofing by checking messages compliance with TDMA protocol.
Digit. Signal Process., May, 2023
2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud.
Behavioral Synthesis for Hardware Security, 2022
2021
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018
2017
J. Syst. Archit., 2017
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
2014
Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging.
Sci. Comput. Program., 2014
A high-level programming model to ease pipeline parallelism expression on shared memory multicore architectures.
Proceedings of the 2014 Spring Simulation Multiconference, 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2010
Proceedings of the Modelling Foundations and Applications - 6th European Conference, 2010
2003
2001
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system.
J. Syst. Archit., 2001