Jean-Christophe Le Lann

Orcid: 0000-0003-2555-1805

Affiliations:
  • ENSTA Bretagne, Brest, France


According to our database1, Jean-Christophe Le Lann authored at least 21 papers between 2001 and 2024.

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Bibliography

2024
An approach to detect identity spoofing in AIS messages.
Expert Syst. Appl., 2024

2023
Detection of AIS messages falsifications and spoofing by checking messages compliance with TDMA protocol.
Digit. Signal Process., May, 2023

2022
HLS-based Accelerated Simulation of Large Scale Cyber-Physical Systems on FPGAs.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud.
Behavioral Synthesis for Hardware Security, 2022

2021
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
LiteX: an open-source SoC builder and library based on Migen Python DSL.
CoRR, 2020

Towards a Hardware DSL Ecosystem : RubyRTL and Friends.
CoRR, 2020

2019
Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
An Integrated Toolchain for Overlay-centric System-on-chip.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

2017
Extended overlay architectures for heterogeneous FPGA cluster management.
J. Syst. Archit., 2017

Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Demo: Overlay architectures for heterogeneous FPGA cluster management.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Communication-Aware Parallelization Strategies for High Performance Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging.
Sci. Comput. Program., 2014

A high-level programming model to ease pipeline parallelism expression on shared memory multicore architectures.
Proceedings of the 2014 Spring Simulation Multiconference, 2014

A prototyping platform for virtual reconfigurable units.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

2012
MHPM: Multi-Scale Hybrid Programming Model: A Flexible Parallelization Methodology.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2010
MoPCoM Methodology: Focus on Models of Computation.
Proceedings of the Modelling Foundations and Applications - 6th European Conference, 2010

2003
POLYCHRONY for System Design.
J. Circuits Syst. Comput., 2003

2001
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system.
J. Syst. Archit., 2001


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