Jedrzej Solecki

According to our database1, Jedrzej Solecki authored at least 13 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Time and Area Optimized Testing of Automotive ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2019
Logic BIST With Capture-Per-Clock Hybrid Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Test Time and Area Optimized BrST Scheme for Automotive ICs.
Proceedings of the IEEE International Test Conference, 2019

2018
Staggered ATPG with capture-per-cycle observation test points.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Trimodal Scan-Based Test Paradigm.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Full-scan LBIST with capture-per-cycle hybrid test points.
Proceedings of the IEEE International Test Conference, 2017

2015
Low-Power Programmable PRPG With Test Compression Capabilities.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A deterministic BIST scheme based on EDT-compressed test patterns.
Proceedings of the 2015 IEEE International Test Conference, 2015

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2012
Low power programmable PRPG with enhanced fault coverage gradient.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs.
J. Electron. Test., 2011

2010
Diagnosis of failing scan cells through orthogonal response compaction.
Proceedings of the 15th European Test Symposium, 2010


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