Justyna Zawada

Orcid: 0000-0002-1881-8164

According to our database1, Justyna Zawada authored at least 14 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Efficient Test Compression Configuration Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.
Proceedings of the IEEE International Test Conference, 2020

Test Challenges of Intel IA Cores.
Proceedings of the IEEE International Test Conference, 2020

2019
Logic BIST With Capture-Per-Clock Hybrid Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
Hardware Protection via Logic Locking Test Points.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

On New Class of Test Points and Their Applications.
Proceedings of the IEEE International Test Conference, 2018

2017
Embedded Deterministic Test Points.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Full-scan LBIST with capture-per-cycle hybrid test points.
Proceedings of the IEEE International Test Conference, 2017

2016
On New Test Points for Compact Cell-Aware Tests.
IEEE Des. Test, 2016

Test point insertion in hybrid test compression/LBIST architectures.
Proceedings of the 2016 IEEE International Test Conference, 2016

On Test Points Enhancing Hardware Security.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Embedded deterministic test points for compact cell-aware tests.
Proceedings of the 2015 IEEE International Test Conference, 2015

Design for low test pattern counts.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Quality assurance in memory built-in self-test tools.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014


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