Tobias Gemmeke
Orcid: 0000-0003-1583-3411
According to our database1,
Tobias Gemmeke
authored at least 64 papers
between 2002 and 2024.
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Bibliography
2024
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024
An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
2023
From neuromorphic to neurohybrid: transition from the emulation to the integration of neuronal networks.
Neuromorph. Comput. Eng., June, 2023
neuroAIx-Framework: design of future neuroscience simulation systems exhibiting execution of the cortical microcircuit model 20× faster than biological real-time.
Frontiers Comput. Neurosci., February, 2023
A Digital Twin Network for Computational Neuroscience Simulators: Exploring Network Architectures for Acceleration of Biological Neural Network Simulations.
Proceedings of the 24th IEEE International Symposium on a World of Wireless, 2023
An Energy-Efficient and Area-Efficient Depthwise Separable Convolution Accelerator with Minimal On-Chip Memory Access.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
DAEBI: A Tool for Data Flow and Architecture Explorations of Binary Neural Network Accelerators.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
neuroAIx: FPGA Cluster for Reproducible and Accelerated Neuroscience Simulations of SNNs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the IEEE Intelligent Vehicles Symposium, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the International Conference on Machine Learning and Applications, 2023
Scalable Time-Domain Compute-in-Memory BNN Engine with 2.06 POPS/W Energy Efficiency for Edge-AI Devices.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous Signals.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IACR Cryptol. ePrint Arch., 2022
Dataflow Optimizations in a Sub-uW Data-Driven TCN Accelerator for Continuous ECG Monitoring.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Multi-Function CIM Array for Genome Alignment Applications built with Fully Digital Flow.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022
All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy Efficiency.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
J. Electron. Test., 2021
Efficiency Versus Accuracy: A Review of Design Techniques for DNN Hardware Accelerators.
IEEE Access, 2021
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Cascaded Classifier for Pareto-Optimal Accuracy-Cost Trade-Off Using Off-the-Shelf ANNs.
Proceedings of the Machine Learning, Optimization, and Data Science, 2021
2020
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Communication architecture enabling 100x accelerated simulation of biological neural networks.
Proceedings of the SLIP '20: System-Level Interconnect, 2020
Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, 2020
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection.
Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2018
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations.
Proceedings of the International Conference on Computer-Aided Design, 2018
A Cortex-M3 Based MCV Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.
ACM Comput. Surv., 2017
Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
2016
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
On the use of analytical techniques for reliability analysis in presence of hardware-induced errors.
Proceedings of the 13th IEEE International Conference on Industrial Informatics, 2015
2014
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the ESSCIRC 2013, 2013
2012
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2007
J. Low Power Electron., 2007
2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
IEEE J. Solid State Circuits, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Optimization of device dimensions for high-performance low-power architecture blocks.
Proceedings of the ESSCIRC 2003, 2003
2002
Implementation of scalable power and area efficient high-throughput Viterbi decoders.
IEEE J. Solid State Circuits, 2002