Jin-Sheng Ren
According to our database1,
Jin-Sheng Ren
authored at least 7 papers
between 2021 and 2024.
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Bibliography
2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips.
IEEE J. Solid State Circuits, January, 2024
2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021