Hongwu Jiang

Orcid: 0000-0002-3048-5948

According to our database1, Hongwu Jiang authored at least 27 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Architecture and Circuit Design Optimization for Compute-In-Memory.
PhD thesis, 2023

Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators.
ACM Trans. Design Autom. Electr. Syst., 2023

2022
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.
ACM Trans. Design Autom. Electr. Syst., 2022

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits, 2022

MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators.
IEEE Des. Test, 2022

A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst., 2021

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell., 2021

Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune.
Proceedings of the 10th IEEE Non-Volatile Memory Systems and Applications Symposium, 2021

Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays.
IEEE Trans. Computers, 2020

8T XNOR-SRAM based Parallel Compute-in-Memory for Deep Neural Network Accelerator.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

MINT: Mixed-Precision RRAM-Based IN-Memory Training Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.
Proceedings of the International Symposium on Memory Systems, 2019


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