Pei-Jung Lu

According to our database1, Pei-Jung Lu authored at least 9 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023

2022
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.
IEEE J. Solid State Circuits, 2022

2021
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips.
IEEE J. Solid State Circuits, 2021

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

DAH: Domain Adapted Deep Image Hashing.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2015
Complementary QA network analysis for QA retrieval in social question-answering websites.
J. Assoc. Inf. Sci. Technol., 2015


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