Hao-Chiao Hong

According to our database1, Hao-Chiao Hong authored at least 31 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2020
Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems.
IEEE Trans. Circuits Syst., 2020

2019
Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Low-voltage indoor energy harvesting using photovoltaic cell.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Gm-C filter with automatic calibration scheme.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2014
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure.
IEEE Trans. Instrum. Meas., 2014

A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform.
J. Electron. Test., 2012

Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure.
Proceedings of the International SoC Design Conference, 2012

2011
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure.
IEEE Trans. Instrum. Meas., 2010

2009
A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Built-in-Self-Test Sigma-Delta ADC Prototype.
J. Electron. Test., 2009

A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
A Cost Effective BIST Second-Order Sigma-Delta-Modulator.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC.
IEEE J. Solid State Circuits, 2007

A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.
J. Electron. Test., 2007

2004
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2002
On-chip Analog Response Extraction with 1-Bit ? - Modulators.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002


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