Hao-Chiao Hong
Orcid: 0000-0003-0757-1001
According to our database1,
Hao-Chiao Hong
authored at least 38 papers
between 2002 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS.
Proceedings of the IEEE International Test Conference in Asia, 2023
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023
2022
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2020
Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems.
IEEE Trans. Circuits Syst., 2020
2019
Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Wireless Gauge Pressure Sensor with Enhanced Sensitivity Fabricated by Flexible PCB Technology For Intracranial Pressure Sensing.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2014
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A Fully Integrated BIST \(\Delta \Sigma \) ADC Using the In-Phase and Quadrature Waves Fitting Procedure.
IEEE Trans. Instrum. Meas., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Electron. Test., 2012
Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure.
Proceedings of the International SoC Design Conference, 2012
2011
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure.
IEEE Trans. Instrum. Meas., 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method.
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC.
IEEE J. Solid State Circuits, 2007
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.
J. Electron. Test., 2007
2006
A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST Systems.
Proceedings of the 15th Asian Test Symposium, 2006
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002