Juan Antonio Clemente
Orcid: 0000-0002-7855-1051
  According to our database1,
  Juan Antonio Clemente
  authored at least 23 papers
  between 2007 and 2024.
  
  
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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    on orcid.org
On csauthors.net:
Bibliography
  2024
Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital.
    
  
    Microprocess. Microsystems, 2024
    
  
  2023
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles.
    
  
    Microprocess. Microsystems, February, 2023
    
  
  2022
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories.
    
  
    IEEE Access, 2022
    
  
  2021
    Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
    
  
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles.
    
  
    Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
    
  
  2020
Impact of Ground-Level Enhancement (GLE) Solar Events on Soft Error Rate for Avionics.
    
  
    IEEE Trans. Aerosp. Electron. Syst., 2020
    
  
Analytical reliability estimation of SRAM-based FPGA designs against single-bit and multiple-cell upsets.
    
  
    Reliab. Eng. Syst. Saf., 2020
    
  
  2018
A decomposition-based reliability and makespan optimization technique for hardware task graphs.
    
  
    Reliab. Eng. Syst. Saf., 2018
    
  
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.
    
  
    IET Comput. Digit. Tech., 2018
    
  
  2017
    IEEE Trans. Very Large Scale Integr. Syst., 2017
    
  
Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable Platforms.
    
  
    IEEE Trans. Aerosp. Electron. Syst., 2017
    
  
  2016
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 2016
    
  
    Neurocomputing, 2016
    
  
  2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
    
  
    IEEE Trans. Very Large Scale Integr. Syst., 2014
    
  
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.
    
  
    ACM Trans. Reconfigurable Technol. Syst., 2014
    
  
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems.
    
  
    ACM Trans. Embed. Comput. Syst., 2014
    
  
  2011
    IEEE Trans. Very Large Scale Integr. Syst., 2011
    
  
    Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
    
  
    Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
    
  
  2010
    Microprocess. Microsystems, 2010
    
  
  2008
    ACM Trans. Design Autom. Electr. Syst., 2008
    
  
    Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
    
  
  2007
HW implementation of an execution manager for reconfigurable systems.
  
    Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007