Po-Yao Chuang

According to our database1, Po-Yao Chuang authored at least 9 papers between 2016 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency.
Proceedings of the IEEE International Test Conference in Asia, 2023

Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023

2022
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2020
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR, 2020

A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018
Covering hard-to-detect defects by thermal quorum sensing.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Cell-aware test generation time reduction by using switch-level ATPG.
Proceedings of the International Test Conference in Asia, 2017

2016
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.
Proceedings of the 25th IEEE Asian Test Symposium, 2016


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